Semiconductor device and electronic apparatus

ABSTRACT

External connection terminals  27  which are electrically connected to semiconductor chips  11 - 1, 11 - 2, 12 - 1, 12 - 2  and also protrude beyond the semiconductor chips  11 - 1, 11 - 2, 12 - 1, 12 - 2  are disposed on a substrate  13  of the side to which the plural semiconductor chips  11 - 1, 11 - 2, 12 - 1, 12 - 2  are connected.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and anelectronic apparatus, and particularly to a semiconductor device inwhich plural semiconductor chips are connected on the same substrate,and an electronic apparatus.

RELATED ART

In the related art, system LSI in which memory or an ASIC, etc. aremixed and installed in one semiconductor chip has been developed asminiaturization of a semiconductor device in which a semiconductor chipis installed on a substrate. However, there were problems that thesystem LSI requires time in a development period or an increase inmanufacturing cost.

Therefore, there is a semiconductor device for achieving miniaturizationby closely connecting plural semiconductor chips (for example, memory oran ASIC) with different functions on the same substrate (see FIG. 19).

FIG. 19 is a sectional view of an electronic apparatus comprising asemiconductor device in which plural semiconductor chips with differentfunctions are closely connected on the same substrate.

An electronic apparatus 100 has a semiconductor device 101, a mountingsubstrate 102 and a sealing resin 115 as shown in FIG. 19. Thesemiconductor device 101 has a substrate 103 and semiconductor chips104A, 104B.

The substrate 103 has a base material 105, connection pads 106, 107,wirings 108, 116 and a protective film 109. The connection pads 106, 107and the wirings 108, 116 are disposed on an upper surface 105A of thebase material 105. The connection pads 106 are electrically connected tothe semiconductor chips 104A, 104B. The connection pads 107 areelectrically connected to the mounting substrate 102.

The wiring 108 makes electrical connection between the connection pads106 located in the vicinity of the center of the base material 105. Thewiring 116 makes electrical connection between the connection pads 106and the connection pads 107. The protective film 109 is disposed so asto cover the wirings 108, 116 with the connection pads 106, 107 exposed.

The semiconductor chips 104A, 104B are semiconductor chips withdifferent functions and are chips of, for example, memory or an ASIC.The semiconductor chips 104A, 104B are electrically connected to theconnection pads 106 disposed on the substrate 103. An under fill resin110 for reducing a difference in a thermal expansion coefficient isdisposed between the semiconductor chips 104A, 104B and the substrate103.

The semiconductor device 101 configured as described above is attachedto the mounting substrate 102 by an adhesive 111. Also, the connectionpads 107 and connection pads 113 disposed on the mounting substrate 102are connected by wires 114 (wire bonding connection). Also, thesemiconductor device 101 connected by wire bonding is sealed by thesealing resin 115 for protecting the wires 114 (for example, seeJapanese Patent Unexamined Publication No. 2005-39161).

However, in the related-art semiconductor device 101, there was aproblem that the connection pads 107 are covered with the under fillresin 110 and electrical connection between the semiconductor device 101and the mounting substrate 102 cannot be made.

Also, when the connection pads 107 are placed in a position separatedfrom the semiconductor chips 104A, 104B so that the connection pads 107are not covered with the under fill resin 110, there was a problem thata size (area) of the substrate 103 increases and the semiconductordevice 101 cannot be miniaturized.

Further, it is necessary to dispose the connection pads 113 in aposition separated from the connection pads 107 so that the wires 114can be placed in order to electrically connect the connection pads 107to the connection pads 113 by the wires 114. As a result of that, therewas a problem that a size (area) of the mounting substrate 102 increasesand the electronic apparatus 100 cannot be miniaturized.

Also, when heights of the wires 114 are higher than those of thesemiconductor chips 104A, 104B (when the wires 114 protrude from thesemiconductor chips 104A, 104B), the sealing resin 115 becomes thick, sothat there was a problem that a height H of the electronic apparatus 100increases and the electronic apparatus 100 cannot be miniaturized.

SUMMARY

Embodiments of the present invention provide a semiconductor device andan electronic apparatus capable of achieving miniaturization andimproving reliability of electrical connection between the semiconductordevice and a mounting substrate.

According to one aspect of one or more embodiments of the invention,there is provided a semiconductor device comprising plural semiconductorchips and a substrate having an external connection terminalelectrically connected to the plural semiconductor chips, characterizedin that the external connection terminal is disposed on the substrate ofthe side to which the plural semiconductor chips are connected and alsois protruded beyond the plural semiconductor chips.

According to the invention, by disposing an external connection terminalon a substrate of the side to which plural semiconductor chips areconnected and also protruding the external connection terminal beyondthe plural semiconductor chips, for example, when an under fill resin isdisposed between the plural semiconductor chips and the substrate, aconnection portion (portion electrically connected to a mountingsubstrate etc.) of the external connection terminal is prevented frombeing covered with the under fill resin, so that reliability ofelectrical connection to a semiconductor device can be improved. Also,the external connection terminal is placed closer to the pluralsemiconductor chips than ever before and an area of the substrate isdecreased and the semiconductor device can be miniaturized.

Also, an under fill resin is disposed between the plural semiconductorchips and the substrate, and a part of the external connection terminallocated in the side of the substrate may be covered with the under fillresin. By covering a part of the external connection terminal located inthe side of the substrate with the under fill resin thus, the externalconnection terminal can be reinforced.

Further, the plural semiconductor chips are semiconductor chips withdifferent functions and may be placed mutually closely. By mutuallyclosely placing the plural semiconductor chips with different functionsthus, the plural semiconductor chips can achieve a function near tosystem LSI.

According to another aspect of one or more embodiments of the invention,there is provided an electronic apparatus comprising a semiconductordevice as claimed in any one of claims 1-5, and amounting substratehaving a first connection pad opposed to the external connectionterminal, characterized in that the external connection terminal iselectrically connected to the first connection pad.

According to the invention, by disposing a first connection pad on amounting substrate as opposed to an external connection terminal, anarea of the mounting substrate is decreased and an electronic apparatuscan be miniaturized. Also, the need for a sealing resin which wasrequired in the related-art electronic apparatus for making wire bondingconnection between the semiconductor device and the mounting substrateis eliminated, so that a height of the electronic apparatus can bedecreased. Further, the need for the sealing resin is eliminated, sothat manufacturing cost of the electronic apparatus can be reduced.

Further, the mounting substrate further has a second connection pad, andthe plural semiconductor chips comprise a metal layer on a surfaceopposite to a surface to which the substrate is connected, and thesecond connection pad may be electrically connected to the metal layer.As a result of this, heat accumulated in the plural semiconductor chipscan be radiated efficiently.

Various implementations may include one or more the followingadvantages. For example, a semiconductor device and an electronicapparatus capable of achieving miniaturization and improving reliabilityof electrical connection between the semiconductor device and a mountingsubstrate can be provided.

Other features and advantages may be apparent from the followingdetailed description, the accompanying drawings and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device according to a firstembodiment of the invention.

FIG. 2 is a sectional view in a direction of line A-A of thesemiconductor device shown in FIG. 1.

FIG. 3 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (first).

FIG. 4 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (second).

FIG. 5 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (third).

FIG. 6 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (fourth).

FIG. 7 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (fifth).

FIG. 8 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (sixth).

FIG. 9 is a diagram showing a manufacturing step of the semiconductordevice according to the first embodiment (seventh).

FIG. 10 is a sectional view of a semiconductor device according to amodified example of the embodiment.

FIG. 11 is a diagram showing a manufacturing step of the semiconductordevice according to the modified example of the embodiment (first).

FIG. 12 is a diagram showing a manufacturing step of the semiconductordevice according to the modified example of the embodiment (second).

FIG. 13 is a diagram showing a manufacturing step of the semiconductordevice according to the modified example of the embodiment (third).

FIG. 14 is a diagram showing a manufacturing step of the semiconductordevice according to the modified example of the embodiment (fourth).

FIG. 15 is a diagram showing a manufacturing step of the semiconductordevice according to the modified example of the embodiment (fifth).

FIG. 16 is a sectional view of an electronic apparatus comprising asemiconductor device of the embodiment.

FIG. 17 is a sectional view of a semiconductor device according to asecond embodiment of the invention.

FIG. 18 is a sectional view of an electronic apparatus comprising asemiconductor device of the embodiment.

FIG. 19 is a sectional view of an electronic apparatus comprising asemiconductor device in which plural semiconductor chips with differentfunctions are closely connected on the same substrate.

DETAILED DESCRIPTION

Next, embodiments of the invention will be described based on thedrawings.

First Embodiment

FIG. 1 is a plan view of a semiconductor device according to a firstembodiment of the invention, and FIG. 2 is a sectional view in adirection of line A-A of the semiconductor device shown in FIG. 1. InFIG. 1, B shows a region (hereinafter called “a mounting region B”) on asubstrate 13 on which semiconductor chips 11-1, 11-2, 12-1, 12-2 aremounted. Also, in FIG. 2, H1 shows a height (hereinafter called “aheight H1”) of the semiconductor chips 11-1, 11-2, 12-1, 12-2 in thecase of using a surface 17A of a base material 17 as the reference andH2 shows a height (hereinafter called “a height H2”) of externalconnection terminals 27 in the case of using the surface 17A of the basematerial 17 as the reference, respectively.

Referring to FIGS. 2 and 3, a semiconductor device 10 has pluralsemiconductor chips 11-1, 11-2, 12-1, 12-2 (four chips in the presentembodiment) and the substrate 13.

The semiconductor chips 11-1, 11-2 are semiconductor chips withfunctions different from those of the semiconductor chips 12-1, 12-2. Asthe semiconductor chips 11-1, 11-2, for example, a semiconductor chipfor memory can be used and in that case, as semiconductor chips 12-1,12-2, for example, a semiconductor chip for ASIC can be used. Also, as asemiconductor substrate of the semiconductor chips 11-1, 11-2, 12-1,12-2, for example, a silicon substrate can be used. The case of usingthe silicon substrate as the semiconductor substrate of thesemiconductor chips 11-1, 11-2, 12-1, 12-2 will be described below as anexample.

Flip chip connection between the semiconductor chips 11-1, 11-2, 12-1,12-2 and the substrate 13 is made through solder bumps 15 in a statethat the semiconductor chips 11-1, 11-2, 12-1, 12-2 are in a mutuallyclose state.

By connecting the semiconductor chips 11-1, 11-2, 12-1, 12-2 to thesubstrate 13 in the state that the semiconductor chips 11-1, 11-2, 12-1,12-2 are in the close state thus, the semiconductor chips 11-1, 11-2,12-1, 12-2 can achieve a function near to system LSI. A distance a(value indicating the extent of proximity) between the semiconductorchips 11-1, 11-2, 12-1, 12-2 can be set at, for example, 50 μm to 100μm.

Also, by making flip chip connection of the semiconductor chips 11-1,11-2, 12-1, 12-2, a height of the semiconductor device 10 can bedecreased as compared with the case of making wire bonding connection.

An under fill resin 16 is disposed between the semiconductor chips 11-1,11-2, 12-1, 12-2 and the substrate 13. The under fill resin 16 is meansfor reducing a difference between the semiconductor chips 11-1, 11-2,12-1, 12-2 and the substrate 13 in a thermal expansion coefficient. Asthe under fill resin 16, for example, an epoxy resin can be used.

The substrate 13 has a base material 17, connection pads 19, 20, wirings21, 22, a protective film 24, an adhesion layer 25 and the externalconnection terminals 27. The base material 17 is formed in plate shape.Silicon is preferable as material of the base material 17. A differencebetween the substrate 13 and the semiconductor chips 11-1, 11-2, 12-1,12-2 comprising a silicon substrate in a thermal expansion coefficientcan be reduced by using silicon as material of the base material 17.

A plurality of the connection pads 19, 20 and the wirings 21, 22 arerespectively disposed on the surface 17A of the base material 17. Theconnection pads 19 are disposed on the base material 17 so as tocorrespond to the mounting region B of the semiconductor chips 11-1,11-2, 12-1, 12-2. The connection pads 19 are electrically connected tothe semiconductor chips 11-1, 11-2, 12-1, 12-2 through the solder bumps15.

The connection pads 20 are disposed on the base material 17 so as tosurround the mounting region B of the semiconductor chips 11-1, 11-2,12-1, 12-2. The connection pads 20 are means for arranging the externalconnection terminals 27, and are electrically connected to the externalconnection terminals 27 through the adhesion layer 25.

The wiring 21 is disposed in the vicinity of the center of the basematerial 17. The wiring 21 makes electrical connection between theconnection pads 19 connected to the semiconductor chip 11-1 and theconnection pads 19 connected to the semiconductor chip 11-2. Electricalconnection between the semiconductor chips 11-1, 11-2 is made by thiswiring 21. Also, electrical connection between the connection pads 19connected to the semiconductor chip 12-1 and the connection pads 19connected to the semiconductor chip 12-2 is made by the wiring 21 (notshown).

The wiring 22 makes electrical connection between the connection pads 19and the connection pad 20. Electrical connection between the externalconnection terminals 27 and each of the semiconductor chips 11-1, 11-2,12-1, 12-2 is made by this wiring 22. As material of the connection pads19, 20 and the wirings 21, 22, a conductive material can be used andconcretely, Al can be used.

The protective film 24 is disposed so as to cover the wirings 21, 22 andthe surface 17A of the base material 17 with the connection pads 19, 20exposed. As material of the protective film 24, for example, a polyimideresin can be used.

The adhesion layer 25 is disposed on the connection pads 19, 20. Theadhesion layer 25 disposed on the connection pads 19 is means forimproving properties of adhesion between the connection pads 19 and thesolder bumps 15. Also, the adhesion layer 25 disposed on the connectionpads 20 is means for improving properties of adhesion between theconnection pads 20 and the external connection terminals 27. As theadhesion layer 25, for example, a Ti/Cu laminated film in which a Tifilm and a Cu film are sequentially laminated from the side of theconnection pads 19, 20 can be used.

The external connection terminals 27 are columnar conductive membersprotruding beyond the semiconductor chips 11-1, 11-2, 12-1, 12-2, andare disposed on the connection pads 20 on which the adhesion layer 25 isformed. The external connection terminals 27 are electrically connectedto the semiconductor chips 11-1, 11-2, 12-1, 12-2 through the connectionpads 20.

The height H2 of the external connection terminal 27 is set so as tobecome higher than the height H1 of the semiconductor chips 11-1, 11-2,12-1, 12-2 (H2>H1). The external connection terminal 27 is a terminalfor making connection to a mounting substrate such as a motherboard (notshown).

By disposing the external connection terminals 27 protruding beyond thesemiconductor chips 11-1, 11-2, 12-1, 12-2 on the surface 17A of thebase material 17 to which plural semiconductor chips 11-1, 11-2, 12-1,12-2 are connected thus, connection portions 27A (portions electricallyconnected to a mounting substrate etc.) of the external connectionterminals 27 are prevented from being covered with the under fill resin16, so that reliability of electrical connection between thesemiconductor device 10 and a mounting substrate (not shown) can beimproved.

Also, the external connection terminals 27 can be disposed closer to thesemiconductor chips 11-1, 11-2, 12-1, 12-2 than ever before, so that asize (area) of the substrate 13 is decreased and the semiconductordevice 10 can be miniaturized.

Also, a part of the external connection terminal 27 located in the sideof the base material 17 is covered with the under fill resin 16. Bycovering a part of the external connection terminal 27 with the underfill resin 16 thus, the external connection terminal 27 can bereinforced. Also, a position of the external connection terminal 27 onthe substrate 13 can be regulated by this reinforcement.

For example, when the height H1 of the semiconductor chips 11-1, 11-2,12-1, 12-2 is 70 μm, the height H2 of the external connection terminal27 can be set at 200 μm. Also, a diameter R1 of the external connectionterminal 27 can be set at, for example, 200 μm and in this case, anarrangement pitch P of the external connection terminals 27 can be setat, for example, 400 μm. A distance b between each of the semiconductorchips 11-1, 11-2, 12-1, 12-2 and the external connection terminal 27closest to each of the semiconductor chips 11-1, 11-2, 12-1, 12-2 can beset at, for example, 50 μm to 300 μm, preferably, 50 μm. As material ofthe external connection terminal 27, a conductive material can be usedand concretely, Cu can be used.

According to the semiconductor device of the embodiment, by disposingthe external connection terminals 27 protruding beyond the semiconductorchips 11-1, 11-2, 12-1, 12-2 on the surface 17A of the base material 17to which plural semiconductor chips 11-1, 11-2, 12-1, 12-2 withdifferent functions are connected, the connection portions 27A of theexternal connection terminals 27 are prevented from being covered withthe under fill resin 16, so that the external connection terminals 27are placed closer to the semiconductor chips 11-1, 11-2, 12-1, 12-2 thanever before and a size (area) of the substrate 13 is decreased and thesemiconductor device 10 can be miniaturized.

FIGS. 4 to 10 are diagrams showing manufacturing steps of thesemiconductor device according to the first embodiment. In FIGS. 4 to10, the same numerals are assigned to the same components as those ofthe semiconductor device 10 described above.

A manufacturing method of the semiconductor device according to thefirst embodiment will be described with reference to FIGS. 4 to 10.First, in a step of FIG. 3, connection pads 19, 20 and wirings 21, 22are simultaneously formed on a surface 17A of a base material 17. Next,a protective film 24 is formed so as to cover the wirings 21, 22 and thesurface 17A of the base material 17 with the connection pads 19, 20exposed. Concretely, a silicon wafer having plural substrate formationregions (regions in which a substrate 13 is formed) is used as the basematerial 17 and an Al film is formed on the surface 17A of the basematerial 17 by a sputtering method and thereafter, a resist layerpatterned is formed on the Al film and subsequently, the Al film isetched by a dry etching method using the resist layer as a mask and theconnection pads 19, 20 and the wirings 21, 22 are simultaneously formed.The protective film 24 is formed by, for example, applying a polyimideresin by a screen printing method. In addition, the Al film may beformed using a vapor deposition method or a CVD method other than thesputtering method.

Then, in a step of FIG. 4, an adhesion layer 25 is formed so as to coveran upper surface of the structure shown in FIG. 3. As the adhesion layer25, for example, a Ti/Cu laminated film in which a Ti film and a Cu filmare sequentially laminated by a sputtering method can be used. Theadhesion layer 25 may be formed by a vapor deposition method or a CVDmethod, etc. other than the sputtering method.

Then, in a step of FIG. 5, a resist layer 29 having openings 29A isformed on the structure shown in FIG. 4. The openings 29A are openingsfor exposing the adhesion layer 25 formed on the connection pads 20.

Then, in a step of FIG. 6, external connection terminals 27 are formedby precipitating a conductive metal film on the adhesion layer 25exposed to the openings 29A by an electrolytic plating method using theadhesion layer 25 as a power feeding layer. As the conductive metalfilm, for example, a Cu film can be used. A height H2 of the externalconnection terminal 27 can be set at, for example, 200 μm. Also, adiameter R1 of the external connection terminal 27 can be set at, forexample, 200 μm and in this case, an arrangement pitch P of the externalconnection terminals 27 can be set at, for example, 400 μm.

Then, in a step of FIG. 7, the resist layer 29 is removed andthereafter, the adhesion layer 25 disposed in the portion other than theconnection pads 19, 20 is removed. As a result of this, a structurecorresponding to the substrate 13 is formed in each of the substrateformation regions on the silicon wafer.

Then, in a step of FIG. 8, semiconductor chips 11-1, 11-2, 12-1, 12-2are connected through solder bumps 15 on the connection pads 19 on whichthe adhesion layer 25 is disposed (flip chip connection). The solderbump 15 is a bump in which solder disposed on each of the semiconductorchips 11-1, 11-2, 12-1, 12-2 and solder disposed on the adhesion layer25 corresponding to the connection pads 19 are melted. A height H1 ofthe semiconductor chips 11-1, 11-2, 12-1, 12-2 can be set at, forexample, 70 μm. Thereafter, the substrate 13 on which the semiconductorchips 11-1, 11-2, 12-1, 12-2 are mounted is diced by dicing.

Then, in a step of FIG. 9, an under fill resin 16 is filled between thesemiconductor chips 11-1, 11-2, 12-1, 12-2 and the substrate 13 and alsocovers parts of the external connection terminals 27. As the under fillresin 16, for example, an epoxy resin can be used. By the manufacturingmethod described above, the semiconductor device 10 is manufactured.

In this embodiment, the semiconductor device 10 further may be sealed bya sealing resin with the surface 17A of the base material 17 exposed. Bysealing the semiconductor device 10 with the sealing resin, thesemiconductor device 10 is easy to be handled. Further, a thermalexpansion coefficient difference between the whole of the semiconductordevice 10 and a mounting substrate (mounting substrate 61 in FIG. 16) ofan electronic apparatus can be reduced since the whole thermal expansioncoefficient of the semiconductor device 10 sealed by the sealing resinis increased in comparison with the thermal expansion coefficient of thesemiconductor device which is not sealed.

FIG. 10 is a sectional view of a semiconductor device according to amodified example of the embodiment. In FIG. 10, the description isomitted by assigning the same numerals to the same components as thoseof the semiconductor device 10 described in FIGS. 2 and 3.

Referring to FIG. 10, a semiconductor device 45 has semiconductor chips11-1, 11-2, 12-1, 12-2 and a substrate 46.

The substrate 46 is configured in a manner similar to the substrate 13except that conductive members 47 are further disposed in theconfiguration of the substrate 13 described above. The conductivemembers 47 are disposed on an adhesion layer 25 formed on connectionpads 19. The conductive members 47 are electrically connected to thesemiconductor chips 11-1, 11-2, 12-1, 12-2 through solder 48. Athickness of the conductive member 47 can be set at, for example, 15 μmto 20 μm. As material of the conductive member 47, material having goodadhesion to the solder is preferable and, for example, Cu can be used.

By disposing the conductive members 47 on the adhesion layer 25 formedon the connection pads 19 thus, the amount of solder necessary in thecase of connecting the semiconductor chips 11-1, 11-2, 12-1, 12-2 to thesubstrate 46 is decreased and manufacturing cost of the semiconductordevice 45 can be reduced.

In addition, effect similar to that of the semiconductor device 10described above can also be obtained in the semiconductor device 45configured above.

FIGS. 12 to 16 are diagrams showing manufacturing steps of thesemiconductor device according to the modified example of theembodiment. In FIGS. 12 to 16, the same numerals are assigned to thesame components as those of the semiconductor device 45 described above.

Next, a manufacturing method of the semiconductor device 45 according tothe modified example of the embodiment will be described with referenceto FIGS. 12 to 16. First, the structure shown in FIG. 4 is formed by thesteps of FIGS. 4 and 5 described above. Next, in a step of FIG. 11, aresist layer 51 having openings 51A, 51B is formed on the structureshown in FIG. 4. The openings 51A correspond to formation positions ofconductive members 47, and an adhesion layer 25 formed on connectionpads 19 is exposed. The openings 51B correspond to formation positionsof external connection terminals 27, and the adhesion layer 25 formed onconnection pads 20 is exposed.

Then, in a step of FIG. 12, the conductive members 47 are formed in theopenings 51A by precipitating a conductive metal film 52 on the adhesionlayer 25 exposed to the openings 51A, 51B by an electrolytic platingmethod using the adhesion layer 25 as a power feeding layer. As theconductive metal film 52, for example, a Cu film can be used. Also, athickness of the conductive metal film 52 can be set at, for example, 15μm to 20 μm. The resist layer 51 is removed after the conductive members47 are formed. In addition, in FIG. 12, the conductive metal film 52formed on the adhesion layer 25 corresponding to the openings 51A isillustrated as the conductive members 47.

Then, in a step of FIG. 13, a resist layer 53 having openings 53A forexposing the conductive metal film 52 disposed over the connection pads20 is formed and subsequently, a conductive metal film 54 is formed onthe conductive metal film 52 by an electrolytic plating method using theconductive metal film 52 exposed from the openings 53A as a powerfeeding layer. As a result of this, the external connection terminals 27made of the conductive metal film 52 and the conductive metal film 54are formed. Also, a height H2 of the external connection terminal 27using a surface 17A of a base material 17 as the reference can be setat, for example, 200 μm.

Then, in a step of FIG. 14, the resist layer 53 is removed and then, theadhesion layer 25 which is not exposed to the conductive members 47 andthe external connection terminals 27 is removed. Then, in a step of FIG.15, solder 48 is disposed on electrode pads (not shown) of thesemiconductor chips 11-1, 11-2, 12-1, 12-2 and this solder 48 iselectrically connected to the conductive members 47.

By forming the conductive members 47 on the adhesion layer 25 locatedover the connection pads 19 thus, the solder 48 is disposed on only thesemiconductor chips 11-1, 11-2, 12-1, 12-2 and the semiconductor chips11-1, 11-2, 12-1, 12-2 can be connected to the substrate 46, so that theamount of solder necessary for connection is decreased and manufacturingcost of the semiconductor device 45 can be reduced.

Then, the substrate 46 to which the semiconductor chips 11-1, 11-2,12-1, 12-2 are connected is diced by dicing. Thereafter, thesemiconductor device 45 is manufactured by performing processing similarto the step of FIG. 9 described above.

FIG. 16 is a sectional view of an electronic apparatus comprising asemiconductor device of the embodiment. In FIG. 16, the same numeralsare assigned to the same components as those of the semiconductor device10 described above.

Referring to FIG. 16, an electronic apparatus 60 has a semiconductordevice 10 and a mounting substrate 61. The mounting substrate 61 hasconnection pads 62 (first connection pads) and external connectionterminals 63.

The connection pads 62 are disposed on an upper surface 61A of themounting substrate 61 and are placed as opposed to external connectionterminals 27 of the semiconductor device 10. The connection pads 62 areelectrically connected to the external connection terminals 27 of thesemiconductor device 10 through solder 65. Also, the connection pads 62are electrically connected to the external connection terminals 63 by awiring pattern (not shown). As the mounting substrate 61, for example, amotherboard can be used.

According to the electronic apparatus of the embodiment, by disposingthe connection pads 62 on the upper surface 61A of the mountingsubstrate 61 as opposed to the external connection terminals 27 of thesemiconductor device 10, the connection pads 62 are placed inside themounting substrate 61 than ever before and a size (area) of the mountingsubstrate 61 is decreased and the electronic apparatus 60 can beminiaturized.

Also, by connecting the external connection terminals 27 of thesemiconductor device 10 to the connection pads 62 of the mountingsubstrate 61 through the solder 65, the need for the sealing resin 115which was required in the related-art electronic apparatus 100 formaking wire bonding connection between the semiconductor device 101 andthe mounting substrate 102 is eliminated, so that manufacturing cost ofthe electronic apparatus 60 can be reduced and also a height of theelectronic apparatus 60 can be decreased.

In addition, in FIG. 16, the electronic apparatus 60 comprising thesemiconductor device 10 and the mounting substrate 61 has been describedas an example, but effect similar to that of the electronic apparatus 60can also be obtained in an electronic apparatus in which a semiconductor45 is disposed instead of the semiconductor device 10.

Second Embodiment

FIG. 17 is a sectional view of a semiconductor device according to asecond embodiment of the invention. In FIG. 17, the same numerals areassigned to the same components as those of the semiconductor device 10described in the first embodiment.

Referring to FIG. 17, a semiconductor device 70 is configured in amanner similar to the semiconductor device 10 described above exceptthat metal layers 71 are disposed on semiconductor chips 11-1, 11-2,12-1, 12-2. The metal layers 71 are disposed on surfaces of thesemiconductor chips 11-1, 11-2, 12-1, 12-2 opposite to the sideconnected to a substrate 13. As the metal layers 71, for example, aTi/Au laminated film in which a Ti film and an Au film are sequentiallylaminated can be used. In addition, effect similar to that of thesemiconductor device 10 of the first embodiment can also be obtained inthe semiconductor device 70 of the present embodiment.

FIG. 18 is a sectional view of an electronic apparatus comprising asemiconductor device of the embodiment. In FIG. 18, the same numeralsare assigned to the same components as those of the electronic apparatus60 described in the first embodiment.

Referring to FIG. 18, an electronic apparatus 75 has a semiconductordevice 70 and a mounting substrate 76. The mounting substrate 76 isconfigured in a manner similar to the mounting substrate 61 described inthe first embodiment except that connection pads 78 (second connectionpads) are further disposed. The connection pads 78 are placed as opposedto the metal layers 71 disposed on the semiconductor chips 11-1, 11-2,12-1, 12-2. The connection pads 78 are electrically connected to themetal layers 71 through solder 79.

According to the electronic apparatus of the embodiment, by disposingthe connection pads 78 on the mounting substrate 76 and electricallyconnecting the connection pads 78 to the metal layers 71 disposed on thesemiconductor chips 11-1, 11-2, 12-1, 12-2 through the solder 79, heatgenerated in the semiconductor chips 11-1, 11-2, 12-1, 12-2 can beradiated efficiently. Also, in the electronic apparatus of theembodiment, similar effect can also be obtained using a semiconductordevice in which the metal layers 71 are disposed on the semiconductorchips 11-1, 11-2, 12-1, 12-2 of the semiconductor device 45 described inFIG. 10 instead of the semiconductor device 70. In addition, effectsimilar to that of the electronic apparatus 60 described in the firstembodiment can also be obtained in the electronic apparatus 75 of theembodiment.

The preferred embodiments of the invention have been described above indetail, but the invention is not limited to such specific embodiments,and various modifications and changes can be made within the gist of theinvention described in the claims.

The invention can be applied to a semiconductor device and an electronicapparatus capable of achieving miniaturization and improving reliabilityof electrical connection between the semiconductor device and a mountingsubstrate.

1. A semiconductor device comprising: a plurality of semiconductorchips; and a substrate having an external connection terminalelectrically connected to said plurality of semiconductor chips, whereinthe external connection terminal is disposed on the substrate of a sideto which the plurality of semiconductor chips are connected and also isprotruded beyond said plurality of semiconductor chips.
 2. Asemiconductor device as claimed in claim 1, wherein the externalconnection terminal is a columnar conductive member.
 3. A semiconductordevice as claimed in claim 1, wherein flip chip connection is madebetween the plurality of semiconductor chips and the substrate of theside on which the external connection terminal is disposed.
 4. Asemiconductor device as claimed in claim 3, wherein an under fill resinis disposed between the plurality of semiconductor chips and thesubstrate, and apart of the external connection terminal located in theside of the substrate is covered with the under fill resin.
 5. Asemiconductor device as claimed in claim 3, wherein said substrate hasconductive members opposed to the plurality of semiconductor chips, eachof said the plurality of the semiconductor chips has a solder disposedthereon, and the flip chip connection is made through the conductormembers and the solders.
 6. A semiconductor device as in claim 1,wherein the plurality of semiconductor chips is semiconductor chips withdifferent functions and is placed mutually closely.
 7. An electronicapparatus comprising: a semiconductor device as claimed in claim 1; anda mounting substrate having a first connection pad opposed to theexternal connection terminal, wherein the external connection terminalis electrically connected to the first connection pad.
 8. An electronicapparatus as claimed in claim 7, wherein the mounting substrate furtherhas a second connection pad, and the plurality of semiconductor chipscomprise a metal layer on a surface opposite to a surface to which thesubstrate is connected, and the second connection pad is electricallyconnected to the metal layer.